Framing Error Detector
Asynchronous serial receivers rely on a high stop bit to frame incoming data bytes correctly. When the line state during the stop bit period is unexpectedly low, it indicates a baud rate mismatch or line corruption.
The circuit monitors the RX line when instructed by the sample_stop signal. If sample_stop is high and RX is low, the framing error flag FE must assert on the next clock edge. The FE flag remains high until the synchronous clear signal is asserted.
| clear | sample_stop | RX | FE (current) | FE (next) | |---------|---------------|------|----------------|-------------| | 1 | X | X | X | 0 | | 0 | 1 | 0 | X | 1 | | 0 | 1 | 1 | X | FE | | 0 | 0 | X | X | FE |
Constraints
- Implement synchronous active-low reset using
rst_n. - Ensure the
clearsignal has strict priority oversample_stop. - Use exactly one D flip-flop to store the
FEstate.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.