UART Receiver Bit Counter
Serial communication protocols require precise tracking of payload boundaries to distinguish data bits from framing bits. A UART receiver relies on a dedicated counter to determine when an entire byte has been shifted in and the stop bit is expected.
The circuit must track the number of received bits and output a 3-bit value count. The counter increments by 1 on the rising edge of clk only when both the data_state flag is high and the baud_tick strobe is active. The counter must synchronously reset to 0 whenever the idle_state flag is asserted, overriding any increment conditions.
| idle_state | data_state | baud_tick | Next count | |--------------|--------------|-------------|--------------| | 1 | 0 | 0 | 0 | | 1 | X | X | 0 | | 0 | 0 | X | count | | 0 | 1 | 0 | count | | 0 | 1 | 1 | count + 1 |
Constraints
- Implement a synchronous 3-bit counter.
- Trigger state updates only on the rising edge of
clk. - Ensure the reset condition is synchronous and takes priority over the increment logic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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