Gated Ring Oscillator
Localized high-frequency clock generation for charge pumps and timing loops relies on ring oscillators. Uncontrolled oscillators burn static power and cause simulation deadlocks. A gated ring oscillator solves this by allowing a control signal to start and stop the oscillation cleanly.
Construct a 3-stage ring oscillator that can be disabled. Replace one inverter in a standard 3-stage ring with a 2-input NAND gate. Connect the en signal to one input of the NAND gate. Tap the output of the final stage (the signal feeding back into the NAND gate) to drive clk_out.
| en | clk_out | |------|-----------| | 0 | 1 | | 1 | Oscillating |
Constraints
- Use exactly one 2-input NAND gate and two NOT gates.
- Form a single continuous combinational loop.
- Do not use external clock sources or flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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