Programmable Duty Cycle Generator
Pulse width modulation forms the backbone of digital motor control and Class-D audio amplifiers. The programmable duty cycle generator produces a periodic signal whose high time is dynamically controlled by a digital input value.
The circuit operates on a continuous 16-cycle period driven by the system clock. For a given 4-bit input duty, the output pwm_out must remain high for the first duty cycles of the 16-cycle period and low for the remaining cycles. If duty is 0, the output remains continuously low. If duty is 15, the output is high for 15 cycles and low for 1 cycle. The internal cycle counter must reset to 0 when rst is asserted high, and pwm_out must be driven to 0 during reset.
Constraints
- Implement a synchronous active-high reset.
- The counter period must be exactly 16 clock cycles.
pwm_outmust evaluate to 0 whenrstis 1.
Topics
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