Rising Edge to Single Cycle Pulse
Synchronous state machines often require single-cycle pulses to trigger state transitions rather than responding to held logic levels. The edge detector circuit converts a sustained input level change into a precise one-clock-cycle pulse.
The circuit receives a clock signal clk and an input signal din. When din transitions from 0 to 1, the output pulse must assert for exactly one clock cycle. If din remains high for multiple cycles, pulse must return to 0 after the first cycle.
| Cycle | din | pulse | |-------|-------|---------| | 0 | 0 | 0 | | 1 | 1 | 1 | | 2 | 1 | 0 | | 3 | 0 | 0 | | 4 | 0 | 0 |
Constraints
- Use exactly one D flip-flop.
- Use standard combinational logic gates to detect the transition.
- The circuit must be fully synchronous to the clock.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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