Falling Edge to Single Cycle Pulse
Button releases, protocol end states, and interrupt clear signals often rely on detecting the removal of a signal. A synchronous edge detector translates a high-to-low transition on an input into a clean, single-cycle pulse.
The circuit must monitor the input d. When d transitions from 1 to 0, the output pulse must assert high for exactly one clock cycle. The logic must operate synchronously on the rising edge of clk.
| Cycle | d | pulse | |-------|-----|---------| | 1 | 1 | 0 | | 2 | 1 | 0 | | 3 | 0 | 1 | | 4 | 0 | 0 | | 5 | 1 | 0 | | 6 | 0 | 1 |
Constraints
- All sequential elements must be clocked on the rising edge of
clk. - Do not use negative edge-triggered flip-flops or latches.
Topics
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