I2C Read Write Bit Extractor
Every I2C device must determine if the master intends to read or write data. The 8th bit of the initial address frame dictates bus ownership for the remainder of the transaction.
This circuit monitors the bus to extract the Read/Write direction bit. The global clock represents the SCL line. The start and stop signals are synchronous single-cycle pulses. The circuit maintains an internal 4-bit register count to track the clock pulses.
| start | stop | count | dir (next) | count (next) | |---------|--------|---------|--------------|----------------| | 1 | X | X | 0 | 0 | | 0 | 1 | X | 0 | 0 | | 0 | 0 | < 7 | dir | count + 1 | | 0 | 0 | 7 | sda | 8 | | 0 | 0 | 8 | dir | 8 |
Constraints
- Implement using sequential logic components.
- Prevent the internal counter from wrapping around to 0 after reaching 8.
- Use only synchronous resets.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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