I2C Device Address Matcher
Every device on an I2C bus observes every transaction, but only the targeted slave must wake up and respond. The address matcher monitors the serial data line following a start condition and flags when the incoming address matches its hardcoded ID.
Construct a 7-bit address matcher for an I2C slave with the hardcoded address 0x5A (binary 1011010). The circuit receives an active-high start signal indicating an I2C Start condition. On the subsequent 7 clock cycles, it shifts in the sda input MSB first. If the received 7-bit sequence equals 1011010, the addressed output must assert high exactly on the 7th clock cycle and remain high until the next start pulse or system rst.
Constraints
- The
addressedoutput must only assert high after exactly 7 bits have been processed. - Address matching must be hardcoded to
0x5A. - An active-high
startpulse must reset the internal bit counter and clear theaddressedflag. - An active-high
rstmust asynchronously clear all internal state.
Topics
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