I2C ACK Generator
I2C buses rely on receivers acknowledging successful byte transfers to keep the data flowing. The receiver must pull the data line low at a precise moment to tell the transmitter to continue.
Design a synchronous sequence controller that triggers the acknowledge signal on the 9th clock pulse of a transfer. The circuit tracks the clock cycles following a start pulse and asserts the ack_pull output at the correct time.
Behavioral contract: * When rst is 1, the circuit enters an idle state. * When start is 1, the circuit begins a new transfer sequence at cycle 0. * While active (not idle), the circuit advances one cycle per clock. * The ack_pull output must be 1 during exactly cycle 9. * On cycle 10, the circuit must return to the idle state and wait for the next start pulse.
Constraints
- All state elements must be synchronous to the rising edge of the clock.
- Do not use asynchronous resets.
- The circuit must hold its idle state indefinitely until
startis asserted.
Topics
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