Incomplete Decoding and Address Aliasing
Embedded system designers sometimes omit upper address lines in decode logic to reduce gate count and propagation delay.
The circuit provided is an address decoder for a 32-byte SRAM block attached to an 8-bit memory bus, A[7:0]. The decoder logic activates the SRAM chip select, CS, when A[7:6] is 00. Address bit A[5] is completely physically disconnected from the decoding logic. The lower bits A[4:0] route directly to the SRAM address pins.
Determine the memory map behavior and identify all address aliases that map to the same physical memory locations.
Constraints
- The address bus
A[7:0]is exactly 8 bits wide. - The SRAM block contains exactly 32 bytes of physical storage.
- Hexadecimal answers must include the
0xprefix.
Topics
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