Memory Mapped IO Address Decoding
Processors communicate with hardware peripherals by reading and writing to specific reserved memory addresses. An address decoder monitors the system bus and activates a specific peripheral only when its assigned address range is accessed.
The circuit must assert the en output when the top four address bits (A3, A2, A1, A0) exactly match the hexadecimal prefix 0xA. For all other address combinations, en must remain low.
| A3 | A2 | A1 | A0 | en | |------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 |
Constraints
- Implement using only combinational logic gates.
- Do not use any sequential elements or memory blocks.
Topics
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