Two Dimensional Coincident Decoding
Large memory arrays cannot rely on a single massive address decoder due to severe area and delay constraints. Instead, the address is split into row and column components to drive a grid matrix, activating exactly one cell at the intersection.
The circuit must decode a 6-bit address bus addr to assert exactly one of 64 output lines on the cell_out bus. The lower 3 bits addr[2:0] drive the column decoder. The upper 3 bits addr[5:3] drive the row decoder. The active cell output is the logical AND of the corresponding row and column lines.
| addr[5:3] | addr[2:0] | Active cell_out index | |-------------|-------------|-------------------------| | 000 | 000 | 0 | | 000 | 111 | 7 | | 001 | 000 | 8 | | 111 | 111 | 63 |
Constraints
- Use exactly two 3-to-8 decoders.
- Use two-input AND gates for the grid matrix intersections.
- Implement using only combinational logic.
Topics
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