JK Flip-Flop: Construction Directly from SR NAND Latch
Resolving undefined states in memory elements is critical for stable state machines and counters. The JK configuration extends a basic latch by utilizing output feedback to eliminate the forbidden state and introduce a deterministic toggle function.
Construct a level-sensitive (pulse-triggered) JK flip-flop. When CLK is high, the outputs Q and Q_bar must update according to the inputs J and K. When CLK is low, the circuit must hold its current state regardless of changes to J or K.
| J | K | CLK | Q (next) | Q_bar (next) | |-----|-----|-------|------------|----------------| | 0 | 0 | 1 | Q | Q_bar | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 1 | Q_bar | Q | | X | X | 0 | Q | Q_bar |
Constraints
- Use exactly one SR NAND Latch component.
- Use exactly two 3-input AND gates for the input steering logic.
- Route the
QandQ_baroutputs back to the input steering gates to prevent simultaneous SET and RESET commands. - Do not use any edge-triggered flip-flop components.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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