JK Flip-Flop: Race-Around Condition in Pulse-Triggered Version
A pulse-triggered JK flip-flop holds its state when the clock is LOW, but when the clock is HIGH it continuously updates its output based on the current inputs and the previous output state. Four signals are shown: CLK (input, active-HIGH enable), J (input), K (input), and Q (output, initially 0). Trace Q across all 12 time steps.
Constraints
Qupdates with a one-step propagation delay based on the previous state whenCLKis 1.- When
CLKis 0,Qholds its state regardless ofJorK.
Topics
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