JK Flip-Flop: J and K Input Swapped Debug
A JK flip-flop stores a single bit of state and allows for set, reset, and toggle operations synchronized to a clock signal.
Expected behavior:
| J | K | Q_next | |-----|-----|----------| | 0 | 0 | Q | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | ~Q |
Simulation shows Q = 0 after a rising clock edge when inputs are J=1 and K=0. Furthermore, applying J=0 and K=1 produces Q = 1. The toggle operation J=1 and K=1 correctly inverts the current state. The set and reset behaviors are failing. Inspect the circuit and correct the fault.
Constraints
- Do not add new gates or components to the circuit.
- Only modify the existing wire connections to fix the fault.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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