JK Flip-Flop with Synchronous Enable
Control logic often requires state elements that update only on specific cycles without interrupting the global clock tree. The synchronous enable pattern allows a flip-flop to hold its state or accept new inputs based on a control signal, avoiding the severe timing hazards introduced by clock gating.
The circuit must behave as a standard JK flip-flop when EN is 1, and completely hold its current state when EN is 0, regardless of the values on J and K.
| EN | J | K | Q | Q_next | |------|-----|-----|-----|----------| | 0 | 1 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | 0 |
Constraints
- Do not connect
ENto the clock signal. - Gate the
JandKinputs using combinational logic. - Drive the
Qoutput using a single JK flip-flop.
Topics
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