JK Flip-Flop: Construction from DFF via Excitation Equation
Legacy designs and specialized counter architectures often rely on the toggle and set/reset properties of JK flip-flops. Modern cell libraries typically only provide D-type flip-flops, requiring designers to synthesize JK behavior using standard combinational logic and a single D flip-flop.
The circuit must implement the state transitions of a JK flip-flop. On the active clock edge, the next state Q_next depends on the current state Q and the inputs J and K.
| J | K | Q | Q_next | |-----|-----|-----|----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 |
Constraints
- Use exactly one D flip-flop.
- Implement the excitation logic using only basic combinational gates (AND, OR, NOT).
- Do not use any other sequential elements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.