JK Flip-Flop: All Four Input Combinations
A positive-edge-triggered JK flip-flop updates its output based on the values of J and K at every LOW-to-HIGH transition of CLK. Four signals are shown: CLK (clock, period 2), J (set input), K (reset input), and Q (output, initially 0). Trace Q across all 16 time steps.
Constraints
- Evaluate the inputs only on the LOW-to-HIGH transitions of the clock.
- The output holds its current value between clock edges.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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