Johnson Counter: 8-Phase Clock Generator
Multiphase clock generation is essential in phase-locked loops, stepper motor drivers, and high-speed memory interfaces. A Johnson counter paired with combinational decoding provides glitch-free, non-overlapping clock phases from a single reference clock.
Implement a 4-bit Johnson counter and decode its states to generate 8 distinct phase outputs (p0 through p7). The counter advances on the rising edge of clk. When rst is HIGH, the internal state must reset to 0000. Each phase output must be HIGH for exactly one clock cycle out of the 8-cycle sequence.
| Internal State (Q3 Q2 Q1 Q0) | Active Phase | |--------------------------------------|--------------| | 0 0 0 0 | p0 | | 0 0 0 1 | p1 | | 0 0 1 1 | p2 | | 0 1 1 1 | p3 | | 1 1 1 1 | p4 | | 1 1 1 0 | p5 | | 1 1 0 0 | p6 | | 1 0 0 0 | p7 |
Constraints
- Use exactly four D flip-flops to build the internal counter.
- Use exactly eight 2-input logic gates to decode the phases.
- Ensure all phase outputs are non-overlapping.
- Reset the counter to state
0000whenrstis HIGH.
Topics
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