Johnson Counter: Build from 4-Bit SISO
Glitch-free state machines and multi-phase clock generators rely on twisted ring topologies to avoid transition hazards. The Johnson counter provides an 8-state sequence from 4 flip-flops by feeding the inverted output of the final stage back to the input.
Construct a 4-bit Johnson counter using a Serial-In Serial-Out (SISO) shift register structure. The circuit must shift data rightward from Q0 toward Q3 on each rising edge of clk. The inverted output of the final stage must drive the input of the first stage. An asynchronous active-high rst clears all flip-flops to 0.
| clk edge | Q0 | Q1 | Q2 | Q3 | |------------|------|------|------|------| | Initial | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 0 | | 3 | 1 | 1 | 1 | 0 | | 4 | 1 | 1 | 1 | 1 | | 5 | 0 | 1 | 1 | 1 | | 6 | 0 | 0 | 1 | 1 | | 7 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 |
Constraints
- Implement the design using exactly four D flip-flops.
- Drive all flip-flops with the same clock signal
clk. - Connect the asynchronous reset signal
rstto clear all flip-flops. - Ensure the sequence is self-generating without external data inputs.
Topics
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