Johnson Counter: Non-Glitchy Decoded Output During Transition
A 4-bit positive-edge-triggered Johnson counter shifts its state rightward on every LOW-to-HIGH transition of CLK, with the first stage Q3 receiving the inverted output of the last stage Q0.
Four signals are provided: CLK (clock, period 2), and the first three state bits Q3, Q2, and Q1.
Trace the final state bit Q0 across all 12 time steps, assuming an initial value of 0. Additionally, trace two combinational decode signals based on the counter bits: DEC3 (defined as Q1 AND ~Q0) and DEC4 (defined as Q3 AND Q0).
Constraints
Q0captures the value ofQ1at every rising edge ofCLKand holds it until the next rising edge.DEC3andDEC4are purely combinational and must be evaluated at every time step based on the current values of their respective inputs.- A valid Johnson counter state transition changes exactly one bit, guaranteeing glitch-free outputs for 2-input decode gates.
Topics
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