4-Bit Ring Counter: Basic Construction with Initial Preset
Multi-phase clock generators and simple stepping sequencers rely on circulating a single active bit through a series of flip-flops. Without a valid initialization state, a ring counter can power up in an all-zero state and remain permanently locked.
The system requires a 4-bit ring counter that circulates a single active bit continuously. The circuit consists of four flip-flops producing outputs Q3, Q2, Q1, and Q0. The shift path routes Q3 to D0, Q0 to D1, Q1 to D2, and Q2 to D3.
When the active-low signal PRE_bar is 0, the counter must asynchronously initialize to a one-hot state of 1000. When PRE_bar is 1, the counter shifts its state on every rising edge of clk.
| PRE_bar | clk | Q3 | Q2 | Q1 | Q0 | |-----------|-------|------|------|------|------| | 0 | X | 1 | 0 | 0 | 0 | | 1 | ↑ | 0 | 0 | 0 | 1 | | 1 | ↑ | 0 | 0 | 1 | 0 | | 1 | ↑ | 0 | 1 | 0 | 0 | | 1 | ↑ | 1 | 0 | 0 | 0 |
Constraints
- Use exactly four D flip-flops.
- Connect
Q3directly toD0to form the feedback loop. - Implement the asynchronous initialization using only the
PRE_barsignal connected to the flip-flop clear and preset pins. - Do not use any additional combinational logic gates in the data path.
Topics
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