Johnson vs. Ring Counter: Area and Timing Comparison for 8-State Sequence
Control logic often requires generating a sequence of mutually exclusive states to drive datapath operations without glitches.
A state machine must produce an 8-state sequence where exactly one output S0 through S7 is high at any given time. Three distinct architectures are proposed to generate this sequence: a Ring counter, a Johnson counter, and a standard Binary counter paired with a decoder.
The Ring counter architecture requires 8 D-flip-flops. The Johnson counter uses 4 D-flip-flops and requires two-input AND gates (AND2) to decode the sequence. The Binary counter uses 3 D-flip-flops and requires three-input AND gates (AND3) to decode the sequence.
Evaluate the area and timing trade-offs among these three architectures. Determine the most efficient implementation given standard CMOS cell library constraints.
Constraints
- Assume a standard CMOS cell library where a D-flip-flop (
DFF) requires 12 area units. - Assume an
AND2gate requires 4 area units and anAND3gate requires 6 area units. - The decoded state outputs
S0throughS7must be strictly glitch-free.
Topics
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