Missing Else in Combinational Logic
An address decoder asserts an enable signal for valid memory addresses and deasserts it for invalid addresses.
Expected behavior:
| A1 | A0 | EN | |------|------|------| | 0 | 0 | 1 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Simulation shows EN = 1 for input A1=1, A0=1 when transitioning from a previous valid address. The enable output fails to deassert for the invalid address state. Inspect the circuit and correct the fault.
Constraints
- The circuit must be purely combinational.
- Output
ENmust be actively driven to a defined logic level for all input combinations.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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