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Codiode/Problems/Sequential Logic

Unassigned Variable in Nested Conditions

HardLogic CircuitDebug

Complex ALU control blocks must explicitly assign all outputs across every execution branch to prevent unintended state retention. The circuit decodes a 3-bit operation code Op2, Op1, Op0 to generate a carry out flag Cout.

Expected behavior:

| Op2 | Op1 | Op0 | Cout | |-------|-------|-------|--------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 |

Simulation shows Cout = 1 when Op2=1, Op1=1, Op0=1 is executed immediately after Op2=1, Op1=1, Op0=0. The output incorrectly retains its previous value instead of updating to 0. Inspect the circuit and correct the fault.

Constraints

  • Only modify the routing in the final multiplexer stage.
  • Do not add new flip-flops or registers to the design.

Topics

debugmultiplexerslatchescontrol-logic

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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