Mod-10 Counter: Synchronous Reset Decode
Binary-Coded Decimal (BCD) arithmetic blocks and digital clocks rely on counters that wrap at strict decimal boundaries. The atomic element for these systems is a 4-bit counter that increments from 0 to 9 and synchronously resets to 0.
The circuit takes a 1-bit clock clk, a 1-bit active-high synchronous reset rst, and a 1-bit active-high enable en. It drives a 4-bit output Q. When en is high, Q increments on the rising edge of clk. Upon reaching state 9 (1001), the counter must wrap around to 0 (0000) on the next clock edge.
| Current Q | en | rst | Next Q | |---|---|---|---| | X | X | 1 | 0000 | | X | 0 | 0 | Q (hold) | | 0000 to 1000 | 1 | 0 | Q + 1 | | 1001 | 1 | 0 | 0000 |
Constraints
- Use only standard D flip-flops and combinational logic gates.
- Implement the design as a fully synchronous circuit triggered by the rising edge of
clk. - Do not use asynchronous reset pins on the flip-flops to handle the mod-10 wrap condition.
Topics
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