Mod-N Counter: Synchronous vs. Async Reset Terminal State Comparison
Two parallel up-counters evaluate the same reset condition (count == 6), but one resets synchronously on the clock edge while the other resets asynchronously.
Four signals are shown: CLK (clock, positive-edge-triggered, period 2), EN (input, count enable, tied high), Q1_SYNC (output, the 2s bit of the synchronous counter, initially 0), and Q1_ASYNC (output, the 2s bit of the asynchronous counter, initially 0).
Trace Q1_SYNC and Q1_ASYNC across all 16 time steps to compare the terminal state behavior and subsequent counting cycle.
Constraints
- The synchronous counter evaluates the reset condition at the active clock edge and applies the reset on the next rising edge.
- The asynchronous counter clears immediately when the reset condition is met, creating a brief glitch before the next half-cycle.
- Both counters increment on the rising edge of
CLKwhenENis 1. - State 6 in binary is 110.
Q1represents the middle bit.
Topics
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