Mod-3 Counter
Phase-locked loops, frequency dividers, and round-robin arbiters rely on non-power-of-two counters to manage uneven timing cycles. The Mod-3 counter is the fundamental building block for these asymmetric dividers.
Implement a 2-bit synchronous counter that sequences through states 0, 1, and 2. State 3 is unused and serves as a don't-care condition for logic minimization. The circuit must compute the next state (D1, D0) based on the current state (Q1, Q0).
| Q1 | Q0 | D1 | D0 | |------|------|------|------| | 0 | 0 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 1 | X | X |
Constraints
- Use exactly two D flip-flops.
- Implement the next-state logic using only basic combinational gates.
- Use a synchronous
rstsignal to initialize the state to00. - Do not use high-level counter modules or adders.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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