Mod-6 Counter: Next-State Table
State machines and clock dividers frequently require non-power-of-two counting sequences. Deriving the next-state logic directly yields a more gate-efficient design than brute-forcing a standard counter with a synchronous reset gate.
Implement a Modulo-6 counter that increments on every rising edge of clk. The counter must follow the binary sequence 0 to 5, returning to 0 after 5. Use states 6 and 7 as don't-cares to minimize the combinational logic for the D flip-flop inputs. The asynchronous rst signal must initialize the state to 0.
| Q2 | Q1 | Q0 | D2 | D1 | D0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | X | X | X | | 1 | 1 | 1 | X | X | X |
Constraints
- Implement the state register using exactly three D flip-flops.
- Derive and implement the minimized next-state logic using basic logic gates.
- Do not use a standard N-bit counter macro block with a synchronous reset.
- The asynchronous
rstsignal must drive the state to 000 when high.
Topics
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