Mod-6 Counter: Synchronous Reset
Digital clocks and timing circuits rely on non-binary modulo counters to track minutes, seconds, and hours. A modulo-6 counter divides a clock frequency by six, commonly used alongside modulo-10 counters to create base-60 timekeeping blocks.
The circuit maintains a 3-bit output Q that increments on the rising edge of clk. The count sequence must iterate from 0 to 5 and then wrap around to 0. An external active-high reset signal forces Q to 0 on the next rising clock edge regardless of the current state. The transient state 6 (110) must be intercepted by the next-state logic to force a synchronous reset to 000.
| reset | Current Q | Next Q | |---------|-------------|----------| | 1 | X | 000 | | 0 | 000 | 001 | | 0 | 001 | 010 | | 0 | 010 | 011 | | 0 | 011 | 100 | | 0 | 100 | 101 | | 0 | 101 | 000 |
Constraints
- Use only D flip-flops for state retention.
- Implement synchronous reset logic only.
- Ensure state 6 (
110) and state 7 (111) never appear on theQoutput.
Topics
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