Mod-5 Counter: One-Cycle Terminal State Waveform
A synchronous-reset 3-bit counter increments its value by 1 on every LOW-to-HIGH transition of CLK when EN is HIGH. When the counter reaches 5 (101), a synchronous reset forces the state to 0 (000) on the next rising edge of CLK: this reset has priority over EN.
Five signals are shown: CLK (clock, period 2), EN (enable input), and outputs Q2, Q1, Q0 (initially representing 3, or 011).
Trace Q2, Q1, and Q0 across all 16 time steps.
Constraints
- The counter updates only on the LOW-to-HIGH transition of
CLK. - The synchronous reset to 0 occurs exactly one clock cycle after the counter reaches 5.
- The synchronous reset overrides the enable signal.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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