Mod-5 Counter: Synchronous Reset Approach
Phase-locked loops and clock dividers frequently require non-power-of-two division ratios to generate precise frequencies. A modulo-N counter achieves this by truncating the standard binary count sequence.
The circuit is a 3-bit synchronous counter that increments by one on every clock cycle. The count sequence must be 0, 1, 2, 3, 4, and then wrap directly back to 0. To achieve this truncation, the logic must decode state 5 (101) to trigger a reset back to 000.
| Q2 | Q1 | Q0 | Next Q2 | Next Q1 | Next Q0 | |------|------|------|-----------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 |
Constraints
- Use a 3-input NAND gate to decode state 5 (
101). - The NAND output must drive the synchronous reset logic for all flip-flops.
- Do not use asynchronous reset pins for the modulo truncation logic.
Topics
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