Synchronous Counter: Count Sequence Verification
A 4-bit positive-edge-triggered synchronous up-counter increments its binary value on every LOW-to-HIGH transition of the clock, rolling over to 0000 after reaching 1111.
Five signals are shown: CLK (clock, period 2), and four counter outputs Q3 (MSB), Q2, Q1, and Q0 (LSB). All outputs are initially 0.
Trace the outputs Q3, Q2, Q1, and Q0 across all 34 time steps to verify the full 16-state count sequence and the rollover transition.
Constraints
- The counter is strictly positive-edge-triggered. Outputs only change when
CLKtransitions from 0 to 1. - The counter rolls over naturally from 1111 (decimal 15) to 0000 (decimal 0).
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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