Mod-12 Counter: Cascade of Mod-3 and Mod-4
Digital clocks, timers, and multi-digit displays rely on cascaded sub-counters to track time efficiently. Decomposing a large modulus into smaller cascaded stages reduces combinational logic depth and limits fan-in.
The circuit must maintain a 4-bit count output that increments on the rising clock edge when en is high. It resets synchronously to 0 when reset is high. The architecture must decompose the 12 states into a cascade: a Mod-4 sub-counter for the lower two bits and a Mod-3 sub-counter for the upper two bits. The internal terminal count of the Mod-4 stage must act as the enable for the Mod-3 stage. The overall circuit must assert tc high when count is 11.
Constraints
- Build the counter using a separate Mod-4 sub-counter and Mod-3 sub-counter.
- Drive the lower 2 bits of
countfrom the Mod-4 sub-counter. - Drive the upper 2 bits of
countfrom the Mod-3 sub-counter. - Use the terminal count of the Mod-4 stage to enable the Mod-3 stage.
- Implement a synchronous active-high reset for both stages.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.