Mod-9 Counter: 4-Bit Design with Multiple Don't-Cares
Phase-locked loops and digital frequency synthesizers often require non-binary integer division. A Modulo-9 counter serves as a divide-by-9 element: it completes one full cycle every nine clock pulses.
The counter advances its 4-bit state Q[3:0] from 0 to 8 sequentially on each clock cycle. Upon reaching state 8, the next state must wrap around to 0. A synchronous rst signal forces the state to 0 on the next clock edge. States 9 through 15 are unreachable during normal operation. You must treat these invalid states as don't-cares to minimize the combinational logic feeding the flip-flops.
| rst | Q3 | Q2 | Q1 | Q0 | Q3_next | Q2_next | Q1_next | Q0_next | |-------|------|------|------|------|-----------|-----------|-----------|-----------| | 1 | X | X | X | X | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 1 | X | X | X | X | | 0 | 1 | 1 | 1 | 1 | X | X | X | X |
Constraints
- Use exactly four D flip-flops for state storage.
- Implement minimized sum-of-products equations for the next-state logic.
- Treat states 9 through 15 as don't-cares in your minimization.
- Include a synchronous reset
rstthat clears all flip-flops to 0.
Topics
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