Mod-7 Counter: Full Next-State Table Design
Frequency dividers and day-of-week trackers in real-time clocks require non-power-of-two modulo counters. A mod-7 counter sequences through seven distinct states before wrapping, serving as a fundamental building block for specialized state machines.
The circuit must increment its 3-bit state (Q2, Q1, Q0) by one on each clock cycle. Upon reaching state 6 (110), the next state must wrap back to 0 (000). State 7 (111) is unreachable under normal operation and must be treated as a don't-care condition to minimize the next-state logic. The synchronous active-high rst signal forces the state to 000.
| Q2 | Q1 | Q0 | D2 | D1 | D0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | X | X | X |
Constraints
- Use exactly three D flip-flops.
- Implement the next-state logic using combinational gates.
- Treat state 111 as a don't-care to minimize the excitation equations.
- Implement a synchronous active-high reset.
Topics
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