Mod-6 Counter Reset Decode Wrong Bit Debug
A mod-6 counter produces a repeating binary sequence from 0 to 5. It uses three flip-flops with asynchronous reset logic to return to state 0 upon reaching state 6.
Expected behavior:
| Clock | Q2 | Q1 | Q0 | State | |---------|------|------|------|---------| | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | 1 | | 2 | 0 | 1 | 0 | 2 | | 3 | 0 | 1 | 1 | 3 | | 4 | 1 | 0 | 0 | 4 | | 5 | 1 | 0 | 1 | 5 | | 6 | 0 | 0 | 0 | 0 |
Simulation shows the count sequence truncates early. The counter outputs states 0, 1, 2, 3, 4, and then immediately resets to 0. The output Q2=1, Q1=0, Q0=1 is never stably reached. The period is 5 instead of 6. Inspect the circuit and correct the fault.
Constraints
- Modify only the wiring to the reset decode logic.
- Do not change the flip-flop types or clock wiring.
Topics
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