MUX Based Data Synchronization with Enable
Arbitrary multi-bit data cannot safely cross clock domains using standard synchronizers due to routing skew. Instead, a control signal is synchronized to the destination clock domain and used to enable the capture of the stable data bus.
The circuit must transfer an 8-bit data_in bus into a destination domain. The control signal en_a indicates that data is ready on the source side. Synchronize en_a into the destination domain using a two-stage flip-flop synchronizer to produce en_b. Route data_in directly to an 8-bit register. Use en_b to enable this register.
| en_b | data_out (next state) | |--------|-------------------------| | 0 | data_out (hold) | | 1 | data_in |
Constraints
- Use exactly two D flip-flops to synchronize
en_a. - Use an 8-bit register with a multiplexer or clock enable for the data path.
- Do not place synchronization logic on the
data_inbus. - All sequential elements must be synchronously reset by
rst_b.
Topics
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