Data Hold Time Requirements for MUX Sync
A MUX synchronizer transfers a multi-bit data bus across clock domains by passing a valid flag through a two-stage flip-flop synchronizer before using it as a register enable.
Five signals are shown: CLK_B (destination clock, positive-edge-triggered, period 4), VALID_A (source valid flag), DATA (source data bus), and the outputs VALID_SYNC (initially 0) and DATA_OUT (initially 1).
Trace VALID_SYNC (the 2-stage synchronized valid flag) and DATA_OUT (which captures DATA on CLK_B rising edges when VALID_SYNC is HIGH, and holds its value otherwise) across all 16 time steps.
Constraints
VALID_SYNCis the output of the second flip-flop in the synchronizer chain.- Both synchronizer flip-flops and the
DATA_OUTregister are clocked byCLK_B. - Initial states:
VALID_SYNCis 0 andDATA_OUTis 1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.