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Codiode/Problems/Sequential Logic

Feedback Synchronization Loop

MediumLogic CircuitTiming Diagram

A closed-loop control system relies on a positive-edge-triggered transmitter that asserts a request and waits for an acknowledgment. The transmitter asserts REQ HIGH on a LOW-to-HIGH transition of CLK if SEND is HIGH and ACK is LOW. It pulls REQ LOW on a LOW-to-HIGH transition of CLK if ACK is HIGH. Four signals are shown: CLK (clock, period 2), SEND (input command), ACK (feedback input) and REQ (output, initially 0). Trace the REQ signal across all 16 time steps.

Constraints

  • The transmitter is strictly positive-edge-triggered.
  • REQ only updates its state at the exact moment of a LOW-to-HIGH clock transition.
  • Input values are evaluated immediately prior to the clock edge.

Topics

SynchronizationClockingHandshake

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