Glitch on Asynchronous Reset Deassertion
Two positive-edge-triggered D flip-flops (Q0 and Q1) share a data input D and an active-low asynchronous reset RST_N.
Five signals are shown: CLK (clock, period 2), RST_N (active-low reset), D (data input), and Q0 and Q1 (outputs, both initially 0). When RST_N is 0, both outputs immediately become 0 regardless of the clock. When RST_N deasserts exactly on a rising edge of CLK, a recovery time violation occurs. Assume Q0 recovers quickly, exiting reset and capturing D on the violating edge. Assume Q1 recovers slowly, missing the edge and remaining in reset until the next cycle.
Trace Q0 and Q1 across all 10 time steps.
Constraints
- Output values must be 0 or 1.
- Asynchronous reset overrides the clock immediately when asserted (logic 0).
- Only the rising edge of
CLKcaptures data when not in reset.
Topics
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