Reset Synchronizer Build
Robust digital systems require a reset that asserts immediately to prevent erratic behavior but deasserts synchronously. This guarantees the entire clock domain exits reset on the exact same clock edge to avoid setup and hold violations.
The circuit takes an asynchronous active-low reset rst_in and a clock clk. It outputs a synchronized active-low reset rst_out. When rst_in drops to 0, rst_out must immediately drop to 0. When rst_in rises to 1, rst_out must transition to 1 only after two rising edges of clk.
| rst_in | clk | rst_out | |----------|-------|-----------| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 0 (cycle 1)| | 1 | 0 | 0 | | 1 | 1 | 1 (cycle 2)|
Constraints
- Use exactly two D flip-flops.
- Wire
rst_indirectly to the asynchronous clear pins of both flip-flops. - Tie the data input of the first flip-flop to a constant logic high (1).
- Do not use any combinational logic gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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