Multi Domain Reset Sequencing
A cross-domain communication interface requires both the fast and slow clock domains to fully exit reset before data transfer is safe.
Three input signals are provided: CLK_F (fast clock, period 2), CLK_S (slow clock, period 4), and RST_N (global asynchronous active-low reset). Each clock domain uses a standard 2-stage reset synchronizer that asserts its output immediately when RST_N is LOW, and deasserts it synchronously on the second LOW-to-HIGH transition of its local clock after RST_N becomes HIGH.
Trace RST_F_N (fast domain reset), RST_S_N (slow domain reset), and the SAFE signal (which is HIGH only when both synchronized resets are HIGH) across all 16 time steps.
Constraints
- The global reset
RST_Nis active-low and asynchronous. - Each domain's reset synchronizer requires exactly two rising edges of its respective clock to propagate the deassertion of
RST_N. - Initial values for all synchronizer stages and outputs are 0.
Topics
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