Asynchronous FIFO Full Flag Timing
A depth-2 asynchronous FIFO generates its FULL flag in the write clock domain when the internal write count exceeds the synchronized read count by 2. The write count increments on any LOW-to-HIGH WCLK transition where WEN is 1. The asynchronous read pointer R_TOG toggles state on each read. R_TOG is synchronized into the write domain via two cascaded D flip-flops clocked by WCLK to produce R_SYNC. A synchronized read is counted whenever R_SYNC changes state.
Three signals are shown: WCLK (write clock, period 2), WEN (write enable, synchronous) and R_TOG (asynchronous read toggle).
Trace the FULL output across all 16 time steps. Assume all internal counts and initial signal states are 0.
Constraints
FULLupdates immediately upon the evaluation of the internal pointer states at each LOW-to-HIGHWCLKtransition.- The synchronizer introduces exactly two clock edges of latency before a change on
R_TOGaffectsR_SYNC.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.