Asynchronous FIFO Empty Flag Timing
An asynchronous FIFO empty flag EMPTY is generated in the read clock domain to prevent underflow. The flag evaluates to HIGH when the read pointer R_PTR equals the synchronized write pointer. The write pointer W_PTR crosses into the read domain through a two-stage flip-flop synchronizer clocked on the positive edge of R_CLK.
Four signals are shown: R_CLK (clock, period 2), W_PTR (input from write domain), R_PTR (input from read domain), and EMPTY (output). Assume both synchronizer flip-flops are initialized to the value of W_PTR at step 0.
Trace EMPTY across all 16 time steps.
Constraints
- The synchronizer flip-flops update only on the LOW-to-HIGH transition of
R_CLK. EMPTYis a combinational output that updates immediately whenR_PTRor the second synchronizer stage changes.
Topics
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