Pessimistic Almost Full Calculation
A FIFO write domain calculates a pessimistic fill level to prevent overflow across asynchronous clock boundaries.
Four signals are shown: CLK (clock, period 2), WR_EN (write enable input), RD_EN (read enable input from the read domain) and ALMOST_FULL (registered output, initially 0).
At each LOW-to-HIGH transition of CLK, the internal fill level increases by 1 if WR_EN is HIGH, and decreases by 1 if RD_EN was HIGH exactly two clock cycles prior (due to a 2-stage synchronizer delay). The ALMOST_FULL flag updates on every rising edge of CLK to 1 if the newly calculated fill level is 6 or greater, and 0 otherwise.
Assume the initial fill level is 4 and RD_EN was strictly 0 for all cycles before the waveform begins. Trace ALMOST_FULL across all 16 time steps.
Constraints
- The internal fill level must be tracked across clock cycles.
- Read pointer updates are delayed by exactly 2 clock cycles before affecting the write domain fill level.
ALMOST_FULLupdates synchronously on the rising edge ofCLKusing the new fill level.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.