Pointer Crossing Delay Analysis
A 3-stage synchronizer transfers a FIFO pointer bit from a fast write clock domain to a slow read clock domain to calculate crossing delay.
Three signals are provided: WCLK (fast write clock, period 2), RCLK (slow read clock, period 4), and PTR_TGL (pointer toggle input). The output SYNC_OUT is the result of capturing PTR_TGL and passing it through three cascaded positive-edge-triggered D flip-flops clocked by RCLK.
Trace SYNC_OUT across all 16 time steps.
Constraints
SYNC_OUTupdates only on the LOW-to-HIGH transitions ofRCLK.- The synchronizer consists of three cascaded flip-flops.
SYNC_OUTis initially 0.
Topics
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