System Level Clock and Reset Architecture
System boot sequences require orchestrating oscillators, multiplexers, and resets in a strict, safe order. A glitch-free multiplexer synchronizes the SEL input to the falling edge of OSC, allowing MUX_CLK to mirror OSC starting from the first falling edge where SEL is 1. An integrated clock gate (ICG) latches EN while MUX_CLK is LOW, passing MUX_CLK to GATED_CLK only if the latched EN is 1. Finally, a 2-stage synchronizer clocked by GATED_CLK drives SYNC_RST_N: it asserts (0) immediately when ASYNC_RST_N is 0, and deasserts (1) only after two rising edges of GATED_CLK occur while ASYNC_RST_N is 1.
Four input signals are shown: OSC (raw clock, period 2), SEL (multiplexer select), EN (clock gate enable), and ASYNC_RST_N (raw asynchronous reset).
Trace the cascaded output signals MUX_CLK, GATED_CLK, and SYNC_RST_N across all 16 time steps. All outputs are initially 0.
Constraints
MUX_CLKmust remain 0 until enabled by a valid falling edge ofOSC.GATED_CLKmust only output complete clock pulses and cannot glitch mid-cycle.SYNC_RST_Ntransitions to 1 only on the rising edge ofGATED_CLK.
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