Missing ASYNC REG Attribute
A two-stage flip-flop synchronizer safely transfers single-bit control signals across asynchronous clock domains.
Expected behavior:
The input async_in is sampled on the rising edge of the destination clock. The synchronized output sync_out reflects the input state after two clock cycles. The synchronization flip-flops must remain as distinct registers and be placed closely together on the die to resolve metastability.
| Cycle | async_in | sync_out | |-------|------------|------------| | 1 | 1 | 0 | | 2 | 1 | 1 | | 3 | 0 | 1 | | 4 | 0 | 0 |
Silicon validation reveals intermittent data corruption on sync_out during asynchronous clock domain crossings. Post-synthesis timing reports indicate a routing delay of 2.4ns between the first and second synchronization stages. Functional simulation passes, but the post-implementation netlist results in an unacceptable mean time between failures (MTBF) in hardware. Inspect the design and correct the fault.
Constraints
- The circuit must implement a two-stage D flip-flop synchronizer.
- The solution must prevent the synthesis tool from optimizing the registers into a shift-register LUT (SRL).
- The solution must ensure tight placement of the synchronization flip-flops.
Topics
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