Combinational Logic Before Synchronizer
Signals crossing clock domains must be glitch-free to prevent false captures in the destination domain. The circuit computes the logical AND of inputs A and B in the source domain and synchronizes the result to the destination domain.
Expected behavior:
| A | B | Y | |-----|-----|-----| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |
Gate-level simulation with timing delays shows Y = 1 for a single clock cycle when A transitions from 1 to 0 and B transitions from 0 to 1 simultaneously. The expected output for this transition is Y = 0 continuously. Inspect the circuit and correct the fault.
Constraints
- The synchronization chain must use exactly two flip-flops in the destination domain
- Only standard flip-flops and basic logic gates are permitted
- The final output must strictly follow the expected truth table after synchronization delay
Topics
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